TDA9110 Datasheet, PDF (15/29 Pages) STMicroelectronics – LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

TDA9110
OPERATING DESCRIPTION
I - GENERAL CONSIDERATIONS
I.1 - Power Supply
The typical values of the power supply voltages
V_CC and V_DD are 12V and 5V respectively. Perfect
operation is obtained for V_CC between 10.8 and
13.2V and V_DD between 4.5 and 5.5V.
In order to avoid erratic operation of the circuit
during transient phase of VCC switching on, or off,
the value of VCC is monitored and the outputs of
the circuit are inhibited if VCC is less than 7.5V
typically.
Similarly,VDD is monitored and internally set-up
until V_DD reaches 4V (see I²C Control Table for
power on reset).
In order to have a verygood powersupply rejection,
the circuit is internally supplied by several voltage
references(typical value : 8V).Two of thesevoltage
references are externally accessible, one for the
vertical and one for the horizontal part. If needed,
these voltage references can be used (if I_LOAD is
less than 5mA). It is necessary to filter the a.m.
voltage references by external capacitors con-
nected to ground, in order to minimize the noise
and consequently the ”jitter” on vertical and hori-
zontal output signals.
I.2 - I²C Control
TDA9110 belongs to the I²C controlled device fam-
ily. Instead of being controlled by DC voltages on
dedicated control pins, each adjustment can be
done via the I²C Interface.
The I²C bus is a serial bus with a clock and a data
input. Thegeneral functionand thebus protocolare
specified in the Philips-bus data sheets.
The interface (Data and Clock) is TTL-level com-
patible. The internal threshold level of the input
comparator is 2.2V (when VDD is 5V). Spikes (up
to 50ns) are filtered by an integrator and the clock
speed is limited to 400kHz.
The data line (SDA) can be used bidirectionally(i.e.
in read-mode the IC clocks out a reply information
(1 byte) to the micro-processor).
The bus protocol prescribes always a full-byte
transmission. The first byte after the start condition
is used to transmit the IC-address(7 bits-8C) and
the read/write bit (0 write - 1 read).
I.3 - Write Mode
In write mode the second byte sent contains the
subaddress of the selected function to adjust (or
controlsto affect)and the third byte the correspond-
ing data byte.It is possible to send more than one
data byte to the IC. If after the third byte no stop or
start condition is detected, the circuit increments
automaticallyby one the momentary subaddressin
the subaddress counter (auto-increment mode).
So it is possible to transmit immediately the next
data bytes without sending the IC address or
subaddress.It can be useful to reinitialize the whole
controls very quickly (flash manner). This proce-
dure can be finished by a stop condition.
The circuit has 16 adjustment capabilities : 2 for the
Horizontal part, 4 for the Vertical, 2 for the E/W
correction, 2 for the Dynamic Horizontal phase
control,2 for the Moire options, 3 for the Horizontal
and Vertical Dynamic Focus and 1 for the HSize
amplitude control.
15 bits are also dedicated to several controls
(ON/OFF, Synchro Priority, Detection Refresh and
Xray reset).
I.4 - Read Mode
During the read mode the second byte transmits
the reply information.
The reply byte contains the Horizontal and Vertical
Lock/Unlock status, the Xray activation status and,
the Horizontaland Vertical polarity detection.It also
contains the Synchro detection status which is
used by the MCU to assign the Synchro priority.
A stop conditionalways stops all the activities of the
bus decoder and switches to high impedance both
for the data and the clock line (SDA and SCL).
See I²C Subaddress and control tables.
I.5 - Synchro Processor
TheinternalSynchroProcessor allowsthe TDA9110
to accept any kind of input synchro signals :
- separated Horizontal & Vertical TTL-compatible
synchro signals,
- composite Horizontal &Vertical TTL-compatible
synchro signals.
I.6 - Synchro Identification Status
The MCU can choose via the I²C the synchro
priority thanks to the system identification status
provided by the TDA9110. The extracted Vertical
synchro pulse is available when this identification
status has been received and when the 12V is
supplied. Even in Power managementmode the IC
is able to inform the MCU that synchrosignals were
detected due to its 5V supply. We recommend to
use the device as following : first, refresh the syn-
chro detection by I²C, then check the status of H/V
det and Vdet by I²C read.
Sync priority choice should be :
Vext H/V
V
Sync priority
Subaddress 03
det det det
D8
D7
Comment
Synchro type
No Yes Yes 1
1 Separated H & V
Yes Yes No 0
1 Composite TTL
H&V
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