DALC208SC6Y Datasheet, PDF (5/12 Pages) STMicroelectronics – Automotive low capacitance diode array for ESD protection

DALC208SC6Y
Technical information
Figure 7. ESD behavior: parasitic phenomena due to unsuitable layout
ESD
SURGE
Lw
Lw ^di
Vf
dt
REF2=+Vcc
Vcl+
167V
Lw ^di
dt
POSITIVE
SURGE
Vcc+Vf
I/O
t
tr=1ns
VI/O
Lw ^di
dt
Vcl+
=
Vcc+Vf+Lw
di
dt
Vcl- =
-Vf-
Lw
di
dt
surge >0
surge <0
tr=1ns
t
-Vf
-Lw ^di
dt
NEGATIVE
SURGE
REF1=GND
-162V
Vcl-
2.3
How to ensure good ESD protection
While the DALC208SC6Y provides a high immunity to ESD surge, an efficient protection
depends on the layout of the board. In the same way, with the rail to rail topology, the track
from the V_REF2 pin to the power supply +V_CC and from the V_REF1 pin to GND must be as short
as possible to avoid over voltages due to parasitic phenomena. See Figure 7.
It’s often harder to connect the power supply near to the DALC208SC6Y unlike the ground
thanks to the ground plane that allows a short connection.
To ensure the same efficiency for positive surges when the connections can’t be short
enough, we recommend putting a capacitance of 100 nF close to the DALC208SC6Y,
between V_REF2 and ground, to prevent these kinds of overvoltage disturbances.
See Figure 8.
The addition of this capacitance will allow a better protection by providing a constant voltage
during a surge.
Figure 9, Figure 10, and Figure 11 show the improvement of the ESD protection according
to the recommendations described above.
Doc ID 16362 Rev 1
5/12