DALC208SC6Y Datasheet, PDF (4/12 Pages) STMicroelectronics – Automotive low capacitance diode array for ESD protection

Technical information
2
Technical information
DALC208SC6Y
2.1
Note:
Surge protection
The DALC208SC6Y is particularly optimized to perform surge protection based on the rail to
rail topology.
The clamping voltage V_CL can be calculated as follow:
V_CL+ = V_REF2 + V_F for positive surges
V_CL- = V_REF1 - V_F for negative surges
with
V_F = V_T + R_d.I_p
(V_F forward drop voltage) / (V_T forward drop threshold voltage)
We assume that the value of the dynamic resistance of the clamping diode is typically
R_d = 0.7  and V_T = 1.2 V.
For an IEC 61000-4-2 surge Level 4 (Contact Discharge: V_g=8 kV, R_g = 330 ), V_REF2 = +5 V,
V_REF1 = 0 V, and if in first approximation, we assume that: I_p = V_g / R_g  24 A.
So, we find:
– V_CL++23 V
– V_CL- -18 V
The calculations do not take into account phenomena due to parasitic inductances.
2.2
Surge protection application example
If we consider that the connections from the pin REF₂ to V_CC and from REF₁ to GND are
done by two tracks of 10 mm long and 0.5 mm large; we assume that the parasitic
inductances of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs, due
to the rise time of this spike (t_r = 1 ns), the voltage V_CL has an extra value equal to Lw.dI/dt.
The dI/dt is calculated as: dI/dt = I_p/t_r  24 A/ns
The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24  144V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be:
– V_CL+ = +23 + 144  167 V
– V_CL- = -18 - 144  -162 V
We can reduce as much as possible these phenomena with simple layout optimization.
It’s the reason why some recommendations have to be followed closely. See Section 2.3:
How to ensure good ESD protection.
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Doc ID 16362 Rev 1