STD7N90K5 Datasheet, PDF (4/16 Pages) STMicroelectronics – Ultra-low gate charge

Electrical characteristics
STD7N90K5
2
Electrical characteristics
TC = 25 °C unless otherwise specified
Table 5: On/off-state
Symbol
Parameter
Test conditions
V(BR)DSS Drain-source breakdown voltage
IDSS Zero gate voltage drain current
IGSS
VGS(th)
RDS(on)
Gate body leakage current
Gate threshold voltage
Static drain-source on-resistance
VGS = 0 V, ID = 1 mA
VGS = 0 V, VDS = 900 V
VGS = 0 V, VDS = 900 V
TC = 125 °C⁽¹⁾
VDS = 0 V, VGS = ±20 V
VDD = VGS, ID = 100 µA
VGS = 10 V, ID = 3.5 A
Min. Typ.
900
3
4
0.72
Max. Unit
V
1 µA
50 µA
±10 µA
5
V
0.81 Ω
Notes:
(1)_{Defined by design, not subject to production test.}
Symbol
Parameter
Table 6: Dynamic
Test conditions
Ciss
Coss
Crss
Co(tr)⁽¹⁾
Co(er)⁽²⁾
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy
related
VDS = 100 V, f = 1
MHz, VGS = 0 V
VGS = 0,
VDS = 0 to 720 V
Rg Intrinsic gate resistance
f = 1 MHz , ID = 0 A
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD = 720 V, ID = 7 A
VGS = 10 V
(see Figure 15: "Test
circuit for gate charge
behavior")
Min. Typ. Max. Unit
- 425 - pF
-
41
-
pF
- 1.2 - pF
-
64
-
pF
24
pF
- 6.7
-
Ω
- 17.7 - nC
- 3.1 - nC
-
13
-
nC
Notes:
(1)_{Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to}
80% VDSS.
(2)_{Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to}
80% VDSS.
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