STM32F469XX Datasheet, PDF (33/217 Pages) STMicroelectronics – ARMCortex-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/384+4KB RAM, USB OTG HS/FS, Ethernet, FMC, dual Quad-SPI, Graphical accelerator, Camera IF, LCD-TFT & MIPI DSI

STM32F469xx
Functional overview
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Operating conditions.The two
2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer
to Section 2.18.
When the regulator is OFF, there is no more internal monitoring on V₁₂. An external power
supply supervisor should be used to monitor the V₁₂ of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V₁₂ power domain.
In regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V₁₂ logic power
domain which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
• The over-drive and under-drive modes are not available.
• The Standby mode is not available.
Figure 10. Regulator OFF
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The following conditions must be respected:
• V_DD should always be higher than V_{CAP_1} and V_{CAP_2} to avoid current injection
between power domains.
• If the time for V_{CAP_1} and V_{CAP_2} to reach V₁₂ minimum value is faster than the time for
V_DD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V_{CAP_1}
and V_{CAP_2} reach V₁₂ minimum value and until V_DD reaches 1.7 V (see Figure 11).
• Otherwise, if the time for V_{CAP_1} and V_{CAP_2} to reach V₁₂ minimum value is slower
than the time for V_DD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 12).
• If V_{CAP_1} and V_{CAP_2} go below V₁₂ minimum value and V_DD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
The minimum value of V₁₂ depends on the maximum frequency targeted in the application
(see Operating conditions).
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