STM32F469XX Datasheet, PDF (176/217 Pages) STMicroelectronics – ARMCortex-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/384+4KB RAM, USB OTG HS/FS, Ethernet, FMC, dual Quad-SPI, Graphical accelerator, Camera IF, LCD-TFT & MIPI DSI

Electrical characteristics
STM32F469xx
Figure 65. Synchronous non-multiplexed NOR/PSRAM read timings
TW#,+
TW#,+
&-#?#,+
TD#,+, .%X,
&-#?.%X
TD#,+, .!$6,
$ATALATENCY
TD#,+, .!$6(
TD#,+( .%X(
&-#?.!$6
&-#?!;=
TD#,+, !6
TD#,+( !)6
TD#,+, ./%,
TD#,+( ./%(
&-#?./%
&-#?$;=
&-#?.7!)4
7!)4#&'B
7!)40/,B
&-#?.7!)4
7!)4#&'B
7!)40/,B
TSU$6 #,+(
TSU.7!)46 #,+(
TH#,+( $6
TSU$6 #,+(
$
$
TH#,+( $6
TH#,+( .7!)46
TSU.7!)46 #,+(
T _{H#,+( .7!)46}
TSU.7!)46 #,+(
TH#,+( .7!)46
-36
Table 98. Synchronous non-multiplexed NOR/PSRAM read timings⁽¹⁾
Symbol
Parameter
Min
Max Unit
t_w(CLK)
FMC_CLK period
t_(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0…2)
t_d(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
t_{d(CLKL-NADVL)} FMC_CLK low to FMC_NADV low
t_{d(CLKL-NADVH)} FMC_CLK low to FMC_NADV high
t_d(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25)
t_d(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25)
t_d(CLKL-NOEL) FMC_CLK low to FMC_NOE low
t_d(CLKH-NOEH) FMC_CLK high to FMC_NOE high
t_su(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high
t_h(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high
t_(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
t_{h(CLKH-NWAIT)} FMC_NWAIT valid after FMC_CLK high
1. Based on test during characterization.
2T_HCLK − 1
-
-
0.5
T_HCLK
-
-
0
0
-
-
0
T_HCLK − 0.5
-
ns
-
T_HCLK+2
T_HCLK − 0.5
-
5
-
0
-
4
-
0
-
176/217
DocID028196 Rev 3