STB3NA60-1 Datasheet, PDF (3/9 Pages) STMicroelectronics – N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR

STB3NA60-1
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symb ol
t_d(on)
tr
(di/ dt) on
Q_g
Q_gs
Q_gd
P a ram et er
Turn-on T ime
Rise Time
Turn-on Current Slope
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
V_DD = 300 V
I_D = 1.5 A
RG = 18 Ω
VGS = 10 V
(see test circuit, figure 3)
VDD = 400 V
ID = 3 A
R_G = 18 Ω
V_GS = 10 V
(see test circuit, figure 5)
I_D = 3 A
V_GS = 10 V
V_DD = Max Rating x 0.8
Min.
Typ .
14
25
300
22
6
9
M a x.
20
35
30
Unit
ns
ns
A/µs
nC
nC
nC
SWITCHING OFF
Symb ol
t_{r(Vo f f)}
tf
t_c
P a ram et er
Off-voltage Rise Time
Fall Time
Cross-over T ime
Test Conditions
V_DD = 480 V
I_D = 3 A
RG = 18 Ω
VGS = 10 V
(see test circuit, figure 5)
Min.
Typ .
13
24
12
M a x.
18
34
17
Unit
ns
ns
ns
SOURCE DRAIN DIODE
Symb ol
P a ram et er
Test Conditions
I_SD
ISDM (•)
Source-drain Current
Source-drain Current
( pu ls ed)
VSD (∗) Forward O n Volt age
ISD = 2.9 A
VGS = 0
t_rr
Reverse Recovery
Time
Q_rr
Reverse Recovery
Charge
I_SD = 3 A
VDD = 100 V
di/dt = 100 A/µs
Tj = 150 ^oC
(see test circuit, figure 5)
I_RRM
Reverse Recovery
Cu r re nt
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Min.
Typ .
460
5.6
24
M a x.
2.9
11.6
1.5
Unit
A
A
V
ns
µC
A
Safe Operating Area
Thermal Impedance
3/9