STBP112 Datasheet, PDF (29/38 Pages) STMicroelectronics – Overvoltage protection device

STBP112
Application information
8.3
PCB layout recommendations
● Input capacitor C1 should be located as close as possible to the STBP112 device.
It should be a low-ESR ceramic capacitor. Also the protective resistors R_FLT and R_EN
(if used) should be located close to the STBP112 (see Figure 4 on page 9).
● For good thermal performance, it is preferred to couple the STBP112 exposed thermal
pads with the PCB ground plane. In most designs, this requires thermal vias between
the copper pads on the PCB and the ground plane.
Doc ID 023357 Rev 3
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