NAND01G-B Datasheet, PDF (26/64 Pages) STMicroelectronics – 1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory

Device operations
NAND01G-B, NAND02G-B
6.2
Cache Read
The Cache Read operation is used to improve the read throughput by reading data using
the Cache Register. As soon as the user starts to read one page, the device automatically
loads the next page into the Cache Register.
An Cache Read operation consists of three steps (see Table 10: Commands):
1. One bus cycle is required to setup the Cache Read command (the same as the
standard Read command)
2. Four or Five (refer to Table 6 and Table 7) bus cycles are then required to input the
Start Address
3. One bus cycle is required to issue the Cache Read confirm command to start the P/E/R
Controller.
The Start Address must be at the beginning of a page (Column Address = 00h, see Table 8
and Table 9). This allows the data to be output uninterrupted after the latency time (t_BLBH1),
see Figure 9
The Ready/Busy signal can be used to monitor the start of the operation. During the latency
period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if
the device is internally downloading page n+1.
Once the Cache Read operation has started, the Status Register can be read using the
Read Status Register command.
During the operation, SR5 can be read, to find out whether the internal reading is ongoing
(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the Cache Register
is ready to download new data.
To exit the Cache Read operation an Exit Cache Read command must be issued (see
Table 10).
If the Exit Cache Read command is issued while the device is internally reading page n+1,
page n will still be output, but not page n+1.
Figure 9. Cache Read Operation
tBLBH1
(Read Busy time)
RB
Busy
I/O
00h
Address
Inputs
31h
Read
Setup
Code
Cache
Read
Confirm
Code
1st page 2nd page 3rd page
last page
Block N
Data Output
34h
Exit
Cache
Read
Code
ai08661
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