NAND01G-B Datasheet, PDF (22/64 Pages) STMicroelectronics – 1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory

Command Set
5
Command Set
NAND01G-B, NAND02G-B
All bus write operations to the device are interpreted by the Command Interface. The
Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is high. Device operations are selected by writing
specific commands to the Command Register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The Commands are summarized in Table 10: Commands.
Table 10. Commands
Command
Bus Write Operations⁽¹⁾⁽²⁾
1^st CYCLE 2^nd CYCLE 3^rd CYCLE 4^th CYCLE
Commands
accepted
during
busy
Read
00h⁽²⁾
30h
–
–
Random Data Output
05h
E0h
–
–
Cache Read
Exit Cache Read
00h
31h
–
34h
–
–
–
–
Yes⁽³⁾
Page Program
80h
10h
–
–
(Sequential Input default)
Random Data Input
85h
–
–
–
Copy Back Program
00h
35h
85h
10h
Cache Program
80h
15h
–
–
Block Erase
60h
D0h
–
–
Reset
FFh
–
–
–
Yes
Read Electronic Signature
90h
–
–
–
Read Status Register
70h
–
–
–
Yes
Read Block Lock Status
7Ah
–
–
–
Blocks Unlock
23h
24h
–
–
Blocks Lock
2Ah
–
–
–
Blocks Lock-Down
2Ch
–
–
–
1. The bus cycles are only shown for issuing the codes. The cycles required to input the
addresses or input/output data are not shown.
2. For consecutive Read operations the 00h command does not need to be repeated.
3. Only during Cache Read busy.
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