STDS75 Datasheet, PDF (22/37 Pages) STMicroelectronics – Digital temperature sensor and thermal watchdog

Functional description
STDS75
3.4.5
Acknowledge
Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse (see Figure 7). A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the High period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line High to enable the master to generate the
STOP condition.
Figure 7. Acknowledgement sequence
START
SCL FROM
MASTER
1
2
CLOCK PULSE FOR
ACKNOWLEDGEMENT
8
9
DATA OUTPUT
BY TRANSMITTER
MSB
LSB
DATA OUTPUT
BY RECEIVER
AI00601
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