STM32F215XX Datasheet, PDF(177/180 Page) STMicroelectronics – Clock, reset and supply management

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STM32F215XX Datasheet, PDF (177/180 Pages) STMicroelectronics – Clock, reset and supply management

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STM32F21xxx

Revision history

Date

29-Oct-2012

Table 94. Document revision history (continued)

Revision

Changes

Removed Figure 4. Compatible board design between STM32F10xx

and STM32F2xx for LQFP176 package.

Updated number of AHB buses in Section 2: Description and

Section 3.12: Clocks and startup.

Updated Note 2 below Figure 4: STM32F21x block diagram.

Changed System memory to System memory + OTP in Figure 14:

Memory map.

Added Note 1 below Table 15: VCAP1/VCAP2 operating conditions.

Updated VDDA and VREF+ decoupling capacitor in Figure 17: Power

supply scheme and updated Note 3.

Changed simplex mode into half-duplex mode in Section 3.24: Inter-

integrated sound (I2S).

Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and

DAC_OUT2, respectively.

Changed TIM2_CH1/TIM2_ETR into TIM2_CH1_ETR for PA0 and PA5

in Table 9: Alternate function mapping.

Updated note applying to IDD (external clock and all peripheral disabled)

in Table 20: Typical and maximum current consumption in Run mode,

code with data processing running from Flash memory (ART

accelerator disabled). Updated Note 3 below Table 21: Typical and

maximum current consumption in Sleep mode.

Removed fHSE_ext typical value in Table 27: High-speed external user

clock characteristics.

Updated master I2S clock jitter conditions and values in Table 34:

8

PLLI2S (audio PLL) characteristics.

Updated equations in Section 6.3.11: PLL spread spectrum clock

generation (SSCG) characteristics.

Swapped TTL and CMOS port conditions for VOL and VOH in Table 46:

Output voltage characteristics. Updated VIL(NRST) and VIH(NRST) in

Table 48: NRST pin characteristics.

Updated Table 53: SPI characteristics and Table 54: I2S

characteristics.Removed note 1 related to measurement points below

Figure 41: SPI timing diagram - slave mode and CPHA = 1, Figure 42:

SPI timing diagram - master mode, and Figure 43: I2S slave timing

diagram (Philips protocol)(1).

Updated tHC in Table 60: ULPI timing.

Updated Figure 47: Ethernet SMI timing diagram, Table 62: Dynamics

characteristics: Ethernet MAC signals for SMI and Table 63: Dynamics

characteristics: Ethernet MAC signals for RMII.

Update fTRIG in Table 65: ADC characteristics. Updated IDDA description

in Table 67: DAC characteristics.

Updated note below Figure 52: Power supply and reference decoupling

(VREF+ not connected to VDDA) and Figure 53: Power supply and

reference decoupling (VREF+ connected to VDDA).

Replaced td(CLKL-NOEL) by td(CLKH-NOEL) in Table 75: Synchronous

multiplexed NOR/PSRAM read timings, Table 77: Synchronous non-

multiplexed NOR/PSRAM read timings, Figure 59: Synchronous

multiplexed NOR/PSRAM read timings and Figure 61: Synchronous

non-multiplexed NOR/PSRAM read timings.

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