STM32F215XX Datasheet, PDF (168/180 Pages) STMicroelectronics – Clock, reset and supply management

Revision history
9
Revision history
STM32F21xxx
Table 94. Document revision history
Date
Revision
Changes
02-Feb-2010
1
Initial release.
13-Jul-2010
Updated datasheet status to PRELIMINARY DATA.
Renamed high-speed SRAM, system SRAM.
Added UFBGA176 package, and note 1 related to LQFP176 package in
Table 2, Figure 12, and Table 93.
Added information on ART accelerator and audio PLL (PLLI2S).
Added Table 5: USART feature comparison.
Several updates on Table 7: STM32F21x pin and ball definitions and
Table 9: Alternate function mapping. ADC, DAC, oscillator, RTC_AF,
WKUP and VBUS signals removed from alternate functions and moved
to the “other functions” column in Table 7: STM32F21x pin and ball
definitions.
TRACESWO added in Figure 4: STM32F21x block diagram, Table 7:
STM32F21x pin and ball definitions, and Table 9: Alternate function
mapping.
XTAL oscillator frequency updated on cover page, in Figure 4:
STM32F21x block diagram and in Section 3.11: External interrupt/event
controller (EXTI).
Updated list of peripherals used for boot mode in Section 3.13: Boot
modes.
Added Regulator bypass mode in Section 3.16: Voltage regulator, and
Section 6.3.4: Operating conditions at power-up / power-down
2
(regulator OFF).
Updated Section 3.17: Real-time clock (RTC), backup SRAM and
backup registers.
Added Note Note: in Section 3.18: Low-power modes.
Added SPI TI protocol in Section 3.23: Serial peripheral interface (SPI).
Updated Section 3.28: Universal serial bus on-the-go full-speed
(OTG_FS), and Section 3.29: Universal serial bus on-the-go high-speed
(OTG_HS).
Added Section 6: Electrical characteristics, and Section 7.6: Thermal
characteristics.
Updated Table 89: LQFP176 - Low profile quad flat package 24 × 24 ×
1.4 mm package mechanical data and Figure 83: LQFP176 - Low
profile quad flat package 24 × 24 × 1.4 mm, package outline.
Added Table 93: Main applications versus package for STM32F2xxx
microcontrollers in A.1: Main applications versus package. Updated
figures in Appendix A.2: USB OTG full speed (FS) interface solutions
and A.3: USB OTG high speed (HS) interface solutions. Updated
Figure 94: Audio player solution using PLL, PLLI2S, USB and 1 crystal
and Figure 95: Audio PLL (PLLI2S) providing accurate I2S clock.
Added random number generation feature. Added trademark for ART
accelerator and updated Section 3.2: Adaptive real-time memory
accelerator (ART Accelerator™).
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