|
STM32F215XX Datasheet, PDF (1/180 Pages) STMicroelectronics – Clock, reset and supply management | |||
|
STM32F215xx
STM32F217xx
ARM®-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, crypto,
USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
Datasheet - production data
Features
⢠Core: ARM® 32-bit Cortex®-M3 CPU (120 MHz
max) with Adaptive real-time accelerator (ART
Acceleratorâ¢) allowing 0-wait state execution
performance from Flash memory, MPU,
150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1)
⢠Memories
â Up to 1 Mbyte of Flash memory
â 512 bytes of OTP memory
â Up to 128 + 4 Kbytes of SRAM
â Flexible static memory controller that
supports Compact Flash, SRAM, PSRAM,
NOR and NAND memories
â LCD parallel interface, 8080/6800 modes
⢠Clock, reset and supply management
â From 1.8 to 3.6 V application supply + I/Os
â POR, PDR, PVD and BOR
â 4 to 26 MHz crystal oscillator
â Internal 16 MHz factory-trimmed RC
â 32 kHz oscillator for RTC with calibration
â Internal 32 kHz RC with calibration
⢠Low-power modes
â Sleep, Stop and Standby modes
â VBAT supply for RTC, 20 Ã 32 bit backup
registers, and optional 4 Kbytes backup
SRAM
⢠3 à 12-bit, 0.5 µs ADCs with up to 24 channels
and up to 6 MSPS in triple interleaved mode
⢠2 à 12-bit D/A converters
⢠General-purpose DMA: 16-stream controller
with centralized FIFOs and burst support
⢠Up to 17 timers
â Up to twelve 16-bit and two 32-bit timers,
up to 120 MHz, each with up to four
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
⢠Debug mode: Serial wire debug (SWD), JTAG,
and Cortex®-M3 Embedded Trace Macrocellâ¢
.
&"'!
LQFP64 (10 Ã 10 mm)
LQFP100 (14 Ã 14 mm)
LQFP144 (20 Ã 20 mm)
LQFP176 (24 Ã 24 mm)
UFBGA176 (10 Ã 10 mm)
â¢
⢠Up to 140 I/O ports with interrupt capability:
â Up to 136 fast I/Os up to 60 MHz
â Up to 138 5 V-tolerant I/Os
⢠Up to 15 communication interfaces
â Up to three I2C interfaces (SMBus/PMBus)
â Up to four USARTs and two UARTs
(7.5 Mbit/s, ISO 7816 interface, LIN, IrDA,
modem control)
â Up to three SPIs (30 Mbit/s), two with
muxed I2S to achieve audio class accuracy
via audio PLL or external PLL
â 2 Ã CAN interfaces (2.0B Active)
â SDIO interface
⢠Advanced connectivity
â USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
â USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
â 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
⢠8- to 14-bit parallel camera interface
(48 Mbyte/s max.)
⢠Cryptographic acceleration
â Hardware acceleration for AES 128, 192,
256, Triple DES, HASH (MD5, SHA-1)
â Analog true random number generator
⢠CRC calculation unit
⢠96-bit unique ID
August 2016
This is information on a product in full production.
DocID17050 Rev 13
1/180
www.st.com
|
▷ |