STM32F302X6 Datasheet, PDF (17/138 Pages) STMicroelectronics – Reset and power management

STM32F302x6 STM32F302x8
Functional overview
3.7
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the high
speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed
APB domain is 36 MHz.
The advanced clock controller clocks the core and all peripherals using a single crystal or
oscillator. To achieve audio class performance, an audio crystal can be used.
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