ST10F271Z1 Datasheet, PDF (169/185 Pages) STMicroelectronics – 16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM

ST10F271Z1
Electrical characteristics
Table 79.
Symbol
Demultiplexed bus timings (continued)
Parameter
F_CPU = 40 MHz
TCL = 12.5 ns
min.
max.
Variable CPU clock
1/2 TCL = 1 to 64 MHz
min.
max.
t₃₈ CC
t₃₉ SR
t₄₁ CC
t₈₂ CC
t₈₃ CC
t₄₆ SR
t₄₇ SR
t₄₈ CC
t₄₉ CC
t₅₀ CC
t₅₁ SR
t₅₃ SR
t₆₈ SR
t₅₅ CC
t₅₇ CC
ALE falling edge to latched
CS
Latched CS low to valid data
In
Latched CS hold after RD,
WR
Address setup to RdCS,
WrCS
(with RW-delay)
Address setup to RdCS,
WrCS
(no RW-delay)
RdCS to valid data in
(with RW-delay)
RdCS to valid data in
(no RW-delay)
RdCS, WrCS low time
(with RW-delay)
RdCS, WrCS low time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay) ³
Data float after RdCS
(no RW-delay) ³
Address hold after
RdCS, WrCS
Data hold after WrCS
– 4 – t_A
–
2 + t_F
14 + 2t_A
2 + 2t_A
–
–
15.5 + t_C
28 + t_C
10 + t_C
0
–
–
– 8.5 + t_F
2 + t_F
6 – t_A
– 4 – t_A
6 – t_A
ns
16.5 +
+ t_C + 2t_A
–
3TCL – 21 +
+ t_C + 2t_A
ns
–
TCL – 10.5 + t_F
–
ns
–
2TCL – 11 + 2t_A
–
ns
–
TCL –10.5 + 2t_A
–
ns
4 + t_C
–
2TCL – 21 + t_C ns
16.5 + t_C
–
3TCL – 21 + t_C ns
–
2TCL – 9.5 + t_C
–
ns
–
–
–
16.5 + t_F
3TCL – 9.5 + t_C
–
ns
2TCL – 15 + t_C
–
ns
0
–
ns
–
2TCL – 8.5 + t_F ns
4 + t_F
–
TCL – 8.5 + t_F ns
–
– 8.5 + t_F
–
ns
–
TCL – 10.5 + t_F
–
ns
1. RW-delay and t_A refer to the next following bus cycle.
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.
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