ST10F271Z1 Datasheet, PDF (100/185 Pages) STMicroelectronics – 16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM

System reset
ST10F271Z1
Table 49. Reset event (continued)
Event
RSTIN
min
max
WDTCON flags
x 0 N Synch.
Not activated
00010
Software reset ⁽²⁾
x 0 N Synch.
0 1 Y Synch.
Not activated
Not activated
00010
00010
1 1 Y Synch.
Activated by internal logic for 1024 TCL
00010
x 0 N Synch.
Not activated
00011
x 0 N Synch.
Watchdog reset ⁽²⁾
0 1 Y Synch.
Not activated
Not activated
00011
00011
1 1 Y Synch.
Activated by internal logic for 1024 TCL
00011
1. It can degenerate into a Long Hardware Reset and consequently differently flagged (see Section 20.3 for details).
2. When Bidirectional is active (and with RPD=0), it can be followed by a Short Hardware Reset and consequently differently
flagged (see Section 20.6 for details).
The start-up configurations and some system features are selected on reset sequences as
described in Table 50 and Figure 35.
Table 50 describes what is the system configuration latched on PORT0 in the six different
reset modes. Figure 35 summarizes the state of bits of PORT0 latched in RP0H, SYSCON,
BUSCON0 registers.
Table 50. PORT0 latched configuration for the different reset events
PORT0
X: Pin is sampled
-: Pin is not sampled
Sample event
Software reset
Watchdog reset
Synchronous short hardware reset
Synchronous long hardware reset
Asynchronous hardware reset
Asynchronous power-on reset
- - - XXXXXXX - - - - - -
- - - XXXXXXX - - - - - -
- - - XXXXXXXXXXXXX
XXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXX
100/185