ST10F271Z1 Datasheet, PDF (161/185 Pages) STMicroelectronics – 16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM

ST10F271Z1
Electrical characteristics
Figure 52. External clock drive XTAL1
t1
t3
t4
VIH2
VIL2
t2
t_OSC
Note:
When Direct Drive is selected, an external clock source can be used to drive XTAL1. The
maximum frequency of the external clock source depends on the duty cycle: when 64MHz is
used, 50% duty cycle shall be granted (low phase = high phase = 7.8 ns); when for instance
32 MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again
equal to 7.8ns).
25.8.14
Memory cycle variables
The tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are to be computed.
Table 77. Memory cycle variables
Description
Symbol
ALE extension
t_A
Memory cycle time wait states
t_C
Memory tri-state time
t_F
Values
TCL x [ALECTL]
2TCL x (15 - [MCTC])
2TCL x (1 - [MTTC])
25.8.15
Note:
External memory bus timing
The following sections include the External Memory Bus timings. The given values are
computed for a maximum CPU clock of 40MHz.
Obviously, when higher CPU clock frequency is used (up to 64MHz), some numbers in the
timing formulas become zero or negative which, in most cases is not acceptable or not
meaningless at all. In these cases, it is necessary to relax the speed of the bus setting
properly t_A, t_C and t_F.
All External Memory Bus Timings and SSC Timings reported in the following tables are
granted by Design Characterization and not fully tested in production.
25.8.16
Multiplexed bus
V_DD = 5 V ± 10%, V_SS = 0V, T_A = –40 to +125 °C, CL = 50 pF,
ALE cycle time = 6 TCL + 2t_A + t_C + t_F (75 ns at 40 MHz CPU clock without wait states)
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