CRX14_10 Datasheet, PDF (16/47 Pages) STMicroelectronics – ISO14443 type-B contactless coupler chip with anti-collision, CRC management and anti-clone function

CRX14 I²C protocol description
4
CRX14 I²C protocol description
CRX14
The CRX14 is compatible with the I²C serial bus memory standard, which is a two-wire
serial interface that uses a bi-directional data bus and serial clock.
The CRX14 has a pre-programmed, 4-bit identification code, ’1010’ (as shown in Table 6),
that corresponds to the I²C bus definition. With this code and the three Chip Enable inputs
(E2, E1, E0) up to eight CRX14 devices can be connected to the I²C bus, and selected
individually.
The CRX14 behaves as a slave device in the I²C protocol, with all CRX14 operations
synchronized to the serial clock.
I²C Read and Write operations are initiated by a START condition, generated by the bus
master.
The START condition is followed by the Device Select Code and by a Read/Write bit (R/W).
It is terminated by an acknowledge bit. The Device Select Code consists of seven bits (as
shown in Table 6):
● the Device Code (first four bits)
● plus three bits corresponding to the states of the three Chip Enable inputs, E2, E1 and
E0, respectively
When data is written to the CRX14, the device inserts an acknowledge bit (9th bit) after the
bus master’s 8-bit transmission.
When the bus master reads data, it also acknowledges the receipt of the data Byte by
inserting an acknowledge bit (9th bit).
Data transfers are terminated by a STOP condition after an ACK for Write, or after a NoACK
for Read.
The CRX14 supports the I²C protocol, as summarized in Figure 6.
Any device that sends data on to the bus, is defined as a transmitter, and any device that
reads the data, as a receiver.
The device that controls the data transfer is known as the master, and the other, as the
slave. A data transfer can only be initiated by the master, which also provides the serial
clock for synchronization. The CRX14 is always a slave device in all I²C communications. All
data are transmitted Most Significant Bit (MSB) first.
Table 6. Device select code
Device code
Chip enable
RW
b7
b6
b5
b4
b3
b2
b1
b0
CRX14 Select
1
0
1
0
E2
E1
E0
RW
4.1
I²C start condition
START is identified by a High-to-Low transition of the Serial Data line, SDA, while the Serial
Clock, SCL, is stable in the High state. A START condition must precede any data transfer
command.
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