STM32L496XX Datasheet, PDF (145/263 Pages) STMicroelectronics – 25 nA Shutdown mode

STM32L496xx
Electrical characteristics
Table 50. Peripheral current consumption (continued)
Peripheral
Range 1
Range 2
Low-power run
and sleep
Unit
APB1
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
USART2 independent clock domain
USART2 APB clock domain
USART3 independent clock domain
USART3 APB clock domain
UART4 independent clock domain
UART4 APB clock domain
UART5 independent clock domain
UART5 APB clock domain
WWDG
All APB1 on
AHB to APB2 bridge⁽⁴⁾
5.85
5.20
4.50
5.60
0.85
0.86
4.06
1.38
4.80
1.80
3.80
1.30
3.83
1.60
0.39
84.20
1.00
4.88
4.25
3.67
4.58
0.70
0.71
3.40
1.17
3.92
1.50
3.10
1.13
3.17
1.25
0.33
74.96
0.90
5.70
5.00
4.20
5.10
0.90
0.90
4.00
1.40
4.60
1.80
3.00
1.30
3.50
1.50
0.40
82.70
0.90
µA/MHz
DFSDM1
6.00
5.00
5.50
FW
0.28
0.30
0.30
SAI1 independent clock domain
2.60
2.10
2.30
SAI1 APB clock domain
2.09
1.80
2.00
SAI2 independent clock domain
3.30
2.70
3.00
SAI2 APB clock domain
2.50
2.00
2.50
SDMMC1 independent clock domain
4.20
3.90
4.20
SDMMC1 APB clock domain
APB2
SPI1
2.10
1.80
2.00
µA/MHz
1.71
1.42
1.50
SYSCFG/VREFBUF/COMP
0.55
0.50
0.50
TIM1
8.41
6.96
7.50
TIM8
8.83
7.33
8.00
TIM15
3.96
3.29
3.50
TIM16
3.24
2.67
3.00
TIM17
2.94
2.46
2.50
USART1 independent clock domain
5.20
4.29
5.50
USART1 APB clock domain
1.70
1.50
1.60
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