STM32F405VGT6 Datasheet, PDF (141/185 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STM32F405xx, STM32F407xx
Electrical characteristics
Table 77. Asynchronous multiplexed PSRAM/NOR read timings⁽¹⁾⁽²⁾ (continued)
t_{v(NADV_NE)}
t_w(NADV)
t_{h(AD_NADV)}
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD(adress) valid hold time after
FSMC_NADV high)
1
2
ns
T_HCLK– 2
T_HCLK+1
ns
T_HCLK
-
ns
t_{h(A_NOE)} Address hold time after FSMC_NOE high
T_HCLK–1
-
ns
t_{h(BL_NOE)} FSMC_BL time after FSMC_NOE high
0
-
ns
t_{v(BL_NE)} FSMC_NEx low to FSMC_BL valid
-
2
ns
t_{su(Data_NE)} Data to FSMC_NEx high setup time
T_HCLK+4
-
ns
t_{su(Data_NOE)} Data to FSMC_NOE high setup time
T_HCLK+4
-
ns
t_{h(Data_NE)} Data hold time after FSMC_NEx high
0
-
ns
t_{h(Data_NOE)} Data hold time after FSMC_NOE high
0
-
ns
1. C_L = 30 pF.
2. Based on characterization, not tested in production.
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms
t_w(NE)
FSMC_NEx
FSMC_NOE
t_{v(NWE_NE)}
t_w(NWE)
t _{h(NE_NWE)}
FSMC_NWE
FSMC_A[25:16]
FSMC_NBL[1:0]
FSMC_AD[15:0]
t_{v(A_NE)}
t_{v(BL_NE)}
t _{v(A_NE)}
Address
t _{v(NADV_NE)}
t_w(NADV)
t_{h(A_NWE)}
Address
t_{h(BL_NWE)}
NBL
t _{v(Data_NADV)}
Data
t_{h(AD_NADV)}
t_{h(Data_NWE)}
FSMC_NADV
ai14891B
Table 78. Asynchronous multiplexed PSRAM/NOR write timings⁽¹⁾⁽²⁾
Symbol
Parameter
Min
Max
Unit
t_w(NE)
t_{v(NWE_NE)}
t_w(NWE)
FSMC_NE low time
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low tim e
4T_HCLK–0.5 4T_HCLK+3 ns
T_HCLK–0.5 T_HCLK -0.5 ns
2T_HCLK–0.5 2T_HCLK+3
ns
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