STM32F405VGT6 Datasheet, PDF (119/185 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STM32F405xx, STM32F407xx
Electrical characteristics
Symbol
Table 55. SPI dynamic characteristics⁽¹⁾ (continued)
Parameter
Conditions
Min
Typ
Max Unit
t_w(SCKH)
t_w(SCKL)
t_su(NSS)
t_h(NSS)
t_su(MI)
t_su(SI)
t_h(MI)
t_h(SI)
t_a(SO)(2)
t_dis(SO)(3)
t_v(SO)
t_h(SO)
t_v(MO)
SCK high and low time
NSS setup time
NSS hold time
Data input setup time
Master mode, SPI presc = 2,
2.7V < V_DD < 3.6V
Master mode, SPI presc = 2,
1.7V < V_DD < 3.6V
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
Master mode
Slave mode
T_PCLK-0.5 T_PCLK T_PCLK+0.5
T_PCLK-2 T_PCLK T_PCLK+2
4 x T_PCLK
-
-
2 x T_PCLK
6.5
-
-
2.5
-
-
Data input hold time
Master mode
Slave mode
2.5
-
-
4
-
-
Data output access time Slave mode, SPI presc = 2
0
Data output disable time
Slave mode, SPI1,
2.7V < V_DD < 3.6V
0
Slave mode, SPI1/2/3
1.7V < V_DD < 3.6V
0
Slave mode (after enable edge),
SPI1, 2.7V < V_DD < 3.6V
-
Slave mode (after enable edge),
Data output valid/hold time ^{SPI2/3, 2.7V < VDD < 3.6V}
-
Slave mode (after enable edge),
SPI1, 1.7V < V_DD < 3.6V
-
Slave mode (after enable edge),
SPI2/3, 1.7V < V_DD < 3.6V
-
Data output valid time
Master mode (after enable edge),
SPI1 , 2.7V < V_DD < 3.6V
-
Master mode (after enable edge),
SPI1/2/3 , 1.7V < V_DD < 3.6V
-
-
4 x T_PCLK
-
7.5
-
16.5
ns
11
13
12
16.5
15.5
19
18
20.5
-
2.5
-
4.5
t_h(MO)
Data output hold time
Master mode (after enable edge)
0
-
-
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
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