LPS001WP Datasheet, PDF (14/30 Pages) STMicroelectronics – MEMS pressure sensor 300-1100 mbar absolute digital output barometer

Digital interfaces
LPS001WP
The I²C interface is compliant with fast mode (400 kHz) I²C standards as well as normal
mode.
6.1.1
I²C operation
The transaction on the bus is started through a START (ST) signal. A start condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
) _{The slave address (SAD) associated to the LPS001WP is 101110xb. The SDO pad can be}
t(s ^{used to modify the less significant bit of the device address. If the SDO pad is connected to}
c ^{voltage supply, LSb is ‘1’ (address 1011101b), otherwise, if the SDO pad is connected to}
u _{ground, the LSb value is ‘0’ (address 1011100b). This solution permits to connect and}
d _{address two different LPS001WPs to the same I}2_{C lines.}
ro _{Data transfer with acknowledge is mandatory. The transmitter must release the SDA line}
P _{during the acknowledge pulse. The receiver must then pull the data line LOW so that it}
te remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
le ^{has been addressed is obliged to generate an acknowledge after each byte of data has}
o been received.
bs The I²C embedded inside the LPS001WP behaves like a slave device and the following
O protocol must be adhered to. After the start condition (ST) a slave address is sent (SAD +
- R/W), once a slave acknowledge (SAK) has been returned, an 8-bit sub-address is
) _{transmitted (SUB): the 7 LSb represent the actual register address while the MSB enables}
t(s ^{address auto increment. If the MSb of the SUB field is 1, the SUB (register address) is}
c ^{automatically incremented to allow a multiple data read/write.}
du ^{The slave address is completed with a read/write bit. If the bit was ‘1’ (Read), a repeated}
ro ^{START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write),}
the master transmits to the slave with an unchanged direction. Table 9 explains how the
P _{SAD+read/write bit pattern is composed, listing all the possible configurations.}
lete_{Table 9. SAD+read/write patterns}
so _Command
SAD[6:1]
SAD[0] = SDO
Ob ^Read
101110
0
R/W
SAD+R/W
1
10111001 (B9h)
Write
101110
0
0
10111000 (B8h)
Read
101110
1
1
10111011 (BBh)
Write
101110
1
0
10111010 (BAh)
Table 10.
Master
Slave
Transfer when master is writing one byte to slave
ST
SAD + W
SUB
DATA
SAK
SAK
SP
SAK
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Doc ID 18171 Rev 1