CLT01-38SQ7 Datasheet, PDF (12/18 Pages) STMicroelectronics – High speed digital input current limiter

Functional description
CLT01-38SQ7
3.3.3
The parity checksum bits calculation and transfer
The aim of the parity checksum bit is to detect one error in the transferred SPI word. Several
parity checksum bits are generated and transmitted through the SPI on the control bit #2 to
#5.
In order to calculate parity bit, “exclusive NOR” operations are performed as follow:
Table 8. CLT01-38SQ7 parity bit calculation example
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
1
0
0
1
1
0
0
1
3.4
PC1
PC2
PC3
PC4
1
1
1
1
Loss of V_CC power supply
The operation of the CLT01-38SQ7 is extended below the levels required in the IEC 61131-
2 standard to allow the implementation of the under voltage alarm UVA as described the SPI
control bit section.
If there is no more power feeding on the V_CC input, the CLT01-38SQ7 chip goes to sleep
mode, and the MISO output is forced in low state during SPI transfer attempt. The last SPI
control data bit is a stop bit placed normally in high state all time: the loss of power supply is
detected by checking its state: if low, the output is disabled by the internal power reset POR.
This POR signal is active in low state when V_C is less than 9V or the internal power supply
V_DD is less than 3.25 V.
Table 9. Logic state of the SPI output versus the power loss signal POR and the SPI
chip select /CS
POR
/CS
MISO
/MISO
SPI status
1
1
Z
Z
Normal with no communication
1
0
1
0
Normal with communication
1
0
0
1
Normal with communication
0
1
Z
Z
Power loss with no communication
0
0
0
1
Power loss with communication attempt
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