CLT01-38SQ7 Datasheet, PDF (11/18 Pages) STMicroelectronics – High speed digital input current limiter

CLT01-38SQ7
Functional description
3.2.2
The SPI data transfer
The CLT01-38SQ7 transfers its 16 data bits through the SPI within one chip select Hi-Lo-Hi
sequence. So, this length defines the minimum length that the shift register of the SPI
master controller is able to capture: 16 bits.
The Table 7 shows the 16-bit mode way the data are transferred starting from the data bits,
the control bits and ending by a stop bit.
Table 7. SPI data transfer organization versus CLT input states with SPM = 0
Bit #
LSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Control High
Low
PC4
PC3
PC2
PC1
/OTA
/UVA
Last out
Bit #
Data
Bit 8
IN 1
Bit 9
IN 2
Bit 10
IN 3
Bit 11
IN 4
Bit 12
IN 5
Bit 13
IN 6
Bit 14
IN 7
MSB
IN 8
First out
3.3
3.3.1
3.3.2
Control bit signals of the SPI transferred data frame
The power bus voltage monitoring
The UVA circuit generates the alarm /UVA that is active low when the power bus voltage is
lower than the activation threshold V_CON, 17 V typical, and it is disabled high when the
power bus voltage rises above the threshold V_COFF, 18 V typical.
The over temperature alarm
The alarm signal /OTA is enabled, low state active, when the junction temperature is higher
than the activation threshold T_ON, 150 ºC typical, and it is disabled when the junction
temperature falls below the threshold T_OFF, 140ºC typical.
DocID028182 Rev 1
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