CLT01-38SQ7 Datasheet, PDF (10/18 Pages) STMicroelectronics – High speed digital input current limiter

Functional description
3
Functional description
CLT01-38SQ7
3.1
Operation of the CLT01-38SQ7 with the SPI bus (C_POL = 0,
C_PHA = 0)
The SPI bus master controller manages the data transfer with the chip select signal /CS and
controls the data shift in the register with the clock SCK signal.
Figure 6. Serial data format frame
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3.1.1
The transfer of the CLT01-38SQ7 input states in the SPI registers starts when the Chip
Select /CS signal falls and ends when this /CS is rising back.
The transfer of data out of the CLT01-38SQ7 slave MISO output starts immediately when
the chip select /CS goes low.
Then, the input MOSI is captured and presented to the shift register on each rising edge of
the clock SCK. And the data are shifted in this register on each falling edge of the serial
clock SCK, the data bits being written on the output MISO with the most significant bit first.
The serial data Input MOSI
This input signal MOSI is used to shift external data bits into the CLT01-38SQ7 register from
the most significant MSB bit to the lower significant one LSB. The data bits are captured by
the CLT01-38SQ7 on the rising edge of the serial clock signal SCK.
3.2
3.2.1
The SPI data transfer operation
The SPI data frame
Depending on the biasing of the SPM pin, the data frame is 8-bits or 16-bits. The selected
structure of the SPI is a 16-bit word in order to be able to implement the input state data and
some control bits such as the UVA alarm, the 4 checksum bits and the two low & high state
stop bits.
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