SST49LF004B_06 Datasheet, PDF (8/36 Pages) Silicon Storage Technology, Inc – 4 Mbit Firmware Hub

Preliminary Specifications
PIN DESCRIPTIONS
4 Mbit Firmware Hub
SST49LF004B
TABLE 1: PIN DESCRIPTION
Symbol Pin Name
Interface
Type¹ PP LPC Functions
LCLK
Clock
I
X To provide a clock input to the control unit.
The clock conforms to the PCI specification.
LAD[3:0] Address and I/O
Data
X To provide LPC bus information such as addresses and command
inputs/outputs to memory.
LFRAME# Frame
MODE
Interface
Mode Select
I
X To indicate start of a data transfer operation; also used to abort an LPC cycle in
progress.
I
X X This pin determines which interface is operational. When held high, programmer
mode is enabled and when held low, LPC mode is enabled. This pin must be set at
power-up or before returning from reset and must not change during device opera-
tion. This pin must be held high (V_IH) for PP mode and low (V_IL) for LPC mode. This
pin is internally pulled-down with a resistor between 20-100 KΩ.
RST#
Reset
I
X X To reset the operation of the device
INIT#
Initialize
I
ID[3:0] Identification
I
Inputs
GPI[4:0] General
I
Purpose Inputs
X This is the second reset pin for in-system use.
This pin functions identically to RST#.
X These four pins are part of the mechanism that allows multiple parts to be attached
to the same bus. The strapping of these pins is used to identify the component. The
boot device must have ID[3:0]=0000, all subsequent devices should use sequential
count-up strapping. These pins are internally pulled-down with a resistor between
20-100 KΩ.
X These individual inputs can be used for additional board flexibility. The state of these
pins can be read through GPI_REG (General Purpose Inputs Register). These
inputs should be at their desired state before the start of the LPC clock cycle during
which the read is attempted, and should remain in place until the end of the Read
cycle. Unused GPI pins must not be floated.
TBL#
WP#
R/C#
Top Block Lock I
Write Protect
I
Row/Column
I
Select
X When low, prevents programming to the boot block sectors at the top of the device
memory. When TBL# is high it disables hardware write protection for the top block
sectors. This pin cannot be left unconnected.
X When low, prevents programming to all but the highest addressable blocks. When
WP# is high it disables hardware write protection for these blocks. This pin cannot be
left unconnected.
X
Select for the Programming interface, this pin determines whether the address pins
are pointing to the row addresses, or to the column addresses.
A₁₀-A₀
Address
I
X
DQ₇-DQ₀ Data
I/O X
OE#
Output Enable I
X
Inputs for low-order addresses during Read and Write operations. Addresses are
internally latched during a Write cycle. For the programming interface, these
addresses are latched by R/C# and share the same pins as the high-order address
inputs.
To output data during Read cycles and receive input data during Write cycles. Data is
internally latched during a Write cycle.
The outputs are in tri-state when OE# is high.
To gate the data output buffers.
WE#
Write Enable
I
X
To control the Write operations.
RES
Reserved
X These pins must be left unconnected.
V_DD
Power Supply PWR X X To provide power supply (3.0-3.6V)
V_SS
Ground
PWR X X Circuit ground (0V reference)
NC
No Connection
N/A N/A Unconnected pins.
1. I = Input, O = Output
T1.2 1307
©2006 Silicon Storage Technology, Inc.
8
S71307-02-000
2/06