SST49LF004B_06 Datasheet, PDF (26/36 Pages) Silicon Storage Technology, Inc – 4 Mbit Firmware Hub

4 Mbit Firmware Hub
SST49LF004B
Preliminary Specifications
TABLE 20: RESET TIMING PARAMETERS, V_DD=3.0-3.6V (PP MODE)
Symbol Parameter
Min
Max
Units
T_PRST
V_DD stable to Reset Low
1
ms
T_RSTP
RST# Pulse Width
100
ns
T_RSTF
RST# Low to Output Float
48
ns
T_RST1
RST# High to Row Address Setup
1
µs
T_RSTE
RST# Low to reset during Sector-/Block-Erase or Program
10
µs
T_RSTC
RST# Low to reset during Chip-Erase
50
µs
T20.0 1307
1. There will be a reset latency of T_RSTE or T_RSTC if a reset procedure is performed during a programming or erase operational.
VDD
Addresses
R/C#
RST#
TPRST
DQ7-0
FIGURE 10: RESET TIMING DIAGRAM (PP MODE)
Row Address
TRSTP
TRSTE
TRSTF
TRSTC
TRST
Sector-/Block-Erase
or Program operation
aborted
Chip-Erase
aborted
1307 F09.0
©2006 Silicon Storage Technology, Inc.
26
S71307-02-000
2/06