SST49LF004B_06 Datasheet, PDF (12/36 Pages) Silicon Storage Technology, Inc – 4 Mbit Firmware Hub

Preliminary Specifications
Firmware Memory Read Cycle
4 Mbit Firmware Hub
SST49LF004B
TABLE 4: FIRMWARE MEMORY READ CYCLE FIELD DEFINITIONS
Clock
Cycle
Field
Name
Field Contents
LAD[3:0]¹
LAD[3:0]
Direction Comments
1
START
1101
IN
LFRAME# must be active (low) for the device to respond.
Only the last field latched before LFRAME# transitions high
will be recognized. The START field contents (1101b) indi-
cate a Firmware Memory Read cycle.
2
IDSEL
0000 to 1111
IN
Indicates which SST49LF004B device should respond. If the
IDSEL (ID select) field matches the value of ID[3:0], the device
will respond to the LPC bus cycle.
3-9
MADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
10
MSIZE
0000 (1 Byte)
IN
The MSIZE field indicates how many bytes will be trans-
ferred during multi-byte operations. The SST49LF004B
only supports single-byte operation. MSIZE=0000b
11
TAR0
1111
IN then Float In this clock cycle, the master has driven the bus to all ‘1’s
and then floats the bus, prior to the next clock cycle. This is
the first part of the bus “turnaround cycle.”
12
TAR1
1111 (float)
Float then The SST49LF004B takes control of the bus during this
OUT
cycle.
13
RSYNC
0000 (READY)
OUT
During this clock cycle, the device generates a “ready sync”
(RSYNC) indicating that the device has received the input
data.
14
DATA
ZZZZ
OUT
ZZZZ is the least-significant nibble of the data byte.
15
DATA
ZZZZ
OUT
ZZZZ is the most-significant nibble of the data byte.
16
TAR0
1111
OUT then
Float
In this clock cycle, the SST49LF004B drives the bus to all
ones and then floats the bus prior to the next clock cycle.
This is the first part of the bus “turnaround cycle.”
17
TAR1
1111 (float)
Float then IN The host resumes control of the bus during this cycle.
1. Field contents are valid on the rising edge of the present clock cycle.
T4.1 1307
LCLK
LFRAME#
LAD[3:0]
Start IDSEL
MADDR
MSIZE TAR0 TAR1 RSYNC
DATA
1101b 0000b A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 0000b 1111b Tri-State 0000b D[3:0] D[7:4] TAR
FIGURE 4: FIRMWARE MEMORY READ CYCLE WAVEFORM
1307 F03.0
©2006 Silicon Storage Technology, Inc.
12
S71307-02-000
2/06