W312-02 Datasheet, PDF (9/19 Pages) Cypress Semiconductor – FTG for VIA K7 Series Chipset with Programmable Output Frequency

W312-02
Byte 9: System Reset and Watchdog Timer Register
Bit
Bit 7
Name
Reserved
Default
0 Reserved
Pin Description
Bit 6
Bit 5
PCI_DRV
Reserved
0 PCI clock output drive strength
0 = Normal
1 = High Drive
0 Reserved
Bit 4
RST_EN_WD
0 This bit will enable the generation of a Reset pulse when a watchdog timer
time-out occurs.
0 = Disabled
1 = Enabled
Bit 3
RST_EN_FC
0 This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled
Bit 2
WD_TO_STATUS
0 Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)
Bit 1
Bit 0
WD_EN
Reserved
0 0 = Stop and re-load Watchdog timer
1 = Enable Watchdog timer. It will start counting down after a frequency change
occurs.
0 Reserved
Byte 10: Skew Control Register
Bit
Name
Bit 7
Bit 6
Bit 5
CPU_Skew2
CPU_Skew1
CPU_Skew0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
PCI_Skew1
PCI_Skew0
AGP_Skew1
AGP_Skew0
Default
0
0
0
0
0
0
0
0
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Reserved
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
AGP skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Description
Rev 1.0, November 27, 2006
Page 9 of 19