W312-02 Datasheet, PDF (7/19 Pages) Cypress Semiconductor – FTG for VIA K7 Series Chipset with Programmable Output Frequency

W312-02
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Byte 3: Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
9
22
–
21
46
–
47
48
Byte 4: Watchdog Timer Register
Bit
Pin#
Bit 7
–
Bit 6
–
Bit 5
–
Bit 4
–
Bit 3
–
Bit 2
–
Bit 1
–
Bit 0
–
Name
PCI_F
PCI9_E
Reserved
PCI8
REF2
Reserved
REF1
REF0
Default
1
1
0
1
1
0
1
1
(Active/Inactive)
(Active/Inactive)
Reserved
(Active/Inactive)
(Active/Inactive)
Reserved
(Active/Inactive)
(Active/Inactive)
Description
Name
Reserved
FS_Override
WD_TIMER4
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
WD_PRE_SCAL
ER
Default
0
0
1
1
1
1
1
0
Description
Reserved
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
These bits store the time-out value of the Watchdog
timer. The scale of the timer is determine by the
prescaler.
The timer can support a value of 150 ms to 4.8 sec
when the prescaler is set to 150 ms. If the prescaler is
set to 2.5 sec, it can support a value from 2.5 sec to 80
sec.
When the Watchdog timer reaches “0”, it will set the
WD_TO_STATUS bit.
0 = 150 ms
1 = 2.5 sec
Byte 5: Control Register 5
Bit
Pin#
Bit 7
9
Bit 6
7
Bit 5
6
Bit 4
47
Bit 3
48
Bit 2
–
Bit 1
–
Bit 0
–
Name
Latched FS4 input
Latched FS3 input
Latched FS2 input
Latched FS1 input
Latched FS0 input
Reserved
Reserved
SEL4
Default
X
X
X
X
X
0
0
0
Description
Latched FS[4:0] inputs. These bits are read only.
Reserved
Reserved
SW Frequency selection bits. See Table 5.
Rev 1.0, November 27, 2006
Page 7 of 19