W312-02 Datasheet, PDF (14/19 Pages) Cypress Semiconductor – FTG for VIA K7 Series Chipset with Programmable Output Frequency

W312-02
Table 6. Register Summary (continued)
Name
RST_EN_WD
RST_EN_FC
Description
This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs.
0 = Disabled
1 = Enabled
This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled
1 = Enabled
How to Program CPU Output Frequency
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:
Fcpu = G * (N+3)/(M+3)
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in Table 5. The ratio of (N+3) and (M+3) need to be
greater than “1” [(N+3)/(M+3) > 1].
Table 7 lists set of N and M values for different frequency
output ranges.This example use a fixed value for the M-Value
Register and select the CPU output frequency by changing the
value of the N-Value Register.
Table 7. Examples of N and M Value for Different CPU Frequency Range
Frequency Ranges
50 MHz–129 MHz
Gear Constants
48.00741
Fixed Value for
M-Value Register
93
130 MHz–248 MHz
48.00741
48
Range of N-Value Register
for Different CPU Frequency
97–255
127–245
Rev 1.0, November 27, 2006
Page 14 of 19