W312-02 Datasheet, PDF (3/19 Pages) Cypress Semiconductor – FTG for VIA K7 Series Chipset with Programmable Output Frequency

W312-02
Pin Definitions (continued)
Pin Name
PD#
Pin No.
34
SDATA
31
SCLK
30
VDD_CPU
40
VDDQ_AGP
25
VDDQ_PCI
VDDQ_48MHz
15, 23
5
VDD_REF
1
VDD_Core
GND_REF,
GND_48MHz,
GND_PCI,
GND_AGP,
GND_Core,
GND_CPU
33
2, 8, 29, 32, 37,
43
Pin
Type
Pin Description
I Power-Down Input: This input will trigger the clock generator into Power Down
mode when it is active.
I/O Data pin for SMBus circuitry.
I Clock pin for SMBus circuitry.
P 2.5V Power Connection: Power supply for CPU output buffers. Connect to
2.5V.
P 3.3V Power Connection: Power supply for AGP output buffers. Connect to
3.3V.
P 3.3V Power Connection: Power supply for PCI output buffers. Connect to 3.3V.
P 3.3V Power Connection: Power supply for 48 MHz output buffers. Connect to
3.3V.
P 3.3V Power Connection: Power supply for reference output buffers. Connect
to 3.3V.
P 3.3V Power Connection: Power supply for PLL core. Connect to 3.3V.
G Ground Connections: Connect all ground pins to the common system ground
plane.
Rev 1.0, November 27, 2006
Page 3 of 19