W196 Datasheet, PDF (9/11 Pages) Cypress Semiconductor – Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

W196
DC Electrical Characteristics: T_A = 0°C to +70°C, V_DDQ3 = 3.3V±5%, V_DDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max. Unit
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required
4. All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section.
5. W196 logic inputs have internal pull-up resistors, except SEL100/66# (pull-ups not full CMOS level).
6. X1 input threshold voltage (typical) is V_DD/2.
7. The W196 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;
this includes typical stray capacitance of short PCB traces to crystal.
8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Pin Capacitance/Inductance
C_IN
C_OUT
L_IN
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
Except X1 and X2
5
pF
6
pF
7
nH
AC Electrical Characteristics
T_A = 0°C to +70°C, V_DDQ3 = 3.3V±5%,V_DDQ2 = 2.5V± 5%, f_XTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
t_P
Period
Measured on rising edge at 1.25V
t_H
High Time
Duration of clock cycle above 2.0V
t_L
Low Time
Duration of clock cycle below 0.4V
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
t_F
Output Fall Edge Rate Measured from 2.0V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at
1.25V
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V.
Maximum difference of cycle time
between two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.25V
f_ST
Frequency Stabili-
Assumes full supply voltage reached
zation from Power-up within 1 ms from power-up. Short cycles
(cold start)
exist prior to frequency stabilization.
Z_o
AC Output Impedance Average value during switching
transition. Used for determining series
termination value.
CPU = 66.8 MHz
Min. Typ. Max.
15
15.5
5.2
5.0
1
4
1
4
45
55
200
175
3
20
CPU = 100 MHz
Min. Typ. Max.
10
10.5
3.0
2.8
1
4
1
4
45
55
250
175
3
20
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ms
:
Rev 1.0, November 28, 2006
Page 9 of 11