W196 Datasheet, PDF (4/11 Pages) Cypress Semiconductor – Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

W196
Functional Description
I/O Pin Operation
Pins 14 and 27 are dual-purpose l/O pins. Upon power-up
these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of these pins is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-k: “strapping” resistor is connected between
the l/O pin and ground or V_DD. Connection to ground sets a
latch to “0”, connection to V_DD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W196 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the REF2X and
24_48MHz clock output buffers are three-stated, allowing the
output strapping resistor on the l/O pin to pull the pin and its
associated capacitive clock load to either a logic HIGH or LOW
state. At the end of the 2-ms period, the established logic “0”
or “1” condition of the l/O pin is then latched. Next the output
buffer is enabled, which converts the l/O pin into an operating
clock output. The 2-ms timer is started when V_DD reaches
2.0V. The input bits can only be reset by turning V_DD off and
then back on again.
It should be noted that the strapping resistors have no signif-
icant effect on clock output signal integrity. The drive
impedance of the clock output is 20: (nominal), which is
minimally affected by the 10-k: strap to ground or V_DD. As
with the series termination resistor, the output strapping
resistor should be placed as close to the l/O pin as possible in
order to keep the interconnecting trace short. The trace from
the resistor to ground or V_DD should be kept less than two
inches in length to prevent system noise coupling during input
logic sampling.
When the clock output is enabled following the 2-ms input
period, a 14.318-MHz output frequency is delivered on the pin,
assuming that V_DD has stabilized. If V_DD has not yet reached
full value, output frequency initially may be below target but will
increase to target once V_DD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
V_DD
Output Strapping Resistor
W196
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Hold
Output
Low
QD
Data
Latch
10 k:
(Load Option 1)
10 k:
(Load Option 0)
Series Termination Resistor
Clock Load
Figure 1. Input Logic Selection Through Resistor Load Option
W196
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Hold
Output
Low
QD
Data
Latch
Jumper Options
10 k:
V_DD
Output Strapping Resistor
Series Termination Resistor
R
Clock Load
Resistor Value R
Figure 2. Input Logic Selection Through Jumper Option
Rev 1.0, November 28, 2006
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