W196 Datasheet, PDF (10/11 Pages) Cypress Semiconductor – Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

W196
PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30 pF
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max.
t_P
Period
Measured on rising edge at 1.5V
30
t_H
High Time
Duration of clock cycle above 2.4V
12
t_L
Low Time
Duration of clock cycle below 0.4V
12
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
1
4
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
1
4
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
t_JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
250
difference of cycle time between two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.5V
500
t_O
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
1
4
edge at 1.5V. CPU leads PCI output.
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
3
from Power-up (cold start) from power-up. Short cycles exist prior to frequency
stabilization.
Z_o
AC Output Impedance Average value during switching transition. Used for
20
determining series termination value.
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
:
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
t_R
Output Rise Edge Rate
t_F
Output Fall Edge Rate
t_D
Duty Cycle
f_ST
Frequency Stabilization
from Power-up (cold start)
Z_o
AC Output Impedance
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.0V
Measured from 2.0V to 0.4V
Measured on rising and falling edge at 1.25V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition. Used
for determining series termination value.
CPU = 66.8/100 MHz
Min. Typ. Max.
14.31818
1
4
1
4
45
55
1.5
15
Unit
MHz
V/ns
V/ns
%
ms
:
REF2X Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Frequency generated by crystal oscillator
t_R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization from Assumes full supply voltage reached within
Power-up (cold start)
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
CPU = 66.8/100 MHz
Min. Typ. Max.
14.318
0.5
2
0.5
2
45
55
3
15
Unit
MHz
V/ns
V/ns
%
ms
:
Rev 1.0, November 28, 2006
Page 10 of 11