W219B Datasheet, PDF (6/14 Pages) Cypress Semiconductor – Frequency Generator for Integrated Core Logic with 133-MHz FSB

W219B
1 bit
7 bits
1
Start bit Slave Address
R/W
1
8 bits
1
Ack
Command Code
Ack
Byte Count = N
Ack Data Byte 1
1 bit
8 bits
Ack
Data Byte 2 Ack
1
8 bits
1
...
Data Byte N
Ack
Stop
8 bits
1
1
Figure 7. An Example of a Block Write^[6]
Serial Data Interface
The W219B features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte with the ability to stop after any
complete byte has been transferred. Indexed bytes are not
allowed.
A block write begins with a slave address and a write condition.
After the command code the core logic issues a byte count
which describes how many more bytes will follow in the
message. If the host had 20 bytes to send, the first byte would
be the number 20 (14h), followed by the 20 bytes of data. The
byte count may not be 0. A block write command is allowed to
transfer a maximum of 32 data bytes. The slave receiver
address for W219B is 11010010. Figure 7 shows an example
of a block write.
The command code and the byte count bytes are required as
the first two bytes of any transfer. W219B expects a command
code of 0000 0000. The byte count byte is the number of
additional bytes required for the transfer, not counting the
command code and byte count bytes. Additionally, the byte
count byte is required to be a minimum of 1 byte and a
maximum of 32 bytes to satisfy the above requirement. Table
2 shows an example of a possible byte count value.
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller. The
command code and byte count bytes are ignored by the
W219B. However, these bytes must be included in the data
write sequence to maintain proper byte allocation.
Table 2. Example of Possible Byte Count Value
Byte Count Byte
MSB
LSB
0000
0000
0000
0001
0000
0010
0000
0011
0000
0100
0000
0101
0000
0110
0000
0111
0010
0000
Notes
Not allowed. Must have at least one byte.
Data for functional and frequency select register (currently byte 0 in spec)
Reads first two bytes of data. (byte 0 then byte1)
Reads first three bytes (byte 0, 1, 2 in order)
Reads first four bytes (byte 0, 1, 2, 3 in order)
Reads first five bytes (byte 0, 1, 2, 3, 4 in order)^[7]
Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)^[7]
Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
Max. byte count supported = 32
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
(Reserved)
Reserved function for future device revision or
production device testing.
Notes:
6. The acknowledgment bit is returned by the slave/receiver (W219B).
7. Bytes 6 and 7 are not defined for W219B.
Common Application
Unused outputs are disabled to reduce EMI and
system power. Examples are clock outputs to unused
PCI slots.
No user application. Register bit must be written as 0.
Rev 1.0, November 20, 2006
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