W219B Datasheet, PDF (1/14 Pages) Cypress Semiconductor – Frequency Generator for Integrated Core Logic with 133-MHz FSB

W219B
Frequency Generator for Integrated Core Logic with 133MHz FSB
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Two copies of CPU clock
• Nine copies of SDRAM clock
• Seven copies of PCI clock
• One copy of synchronous APIC clock
• Three copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• One copy of selectable 24- or 48-MHz clock
• One copy of double strength 14.31818-MHz reference
clock
• Power-down control
• SMBus interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ................................................... 500 ps
CPU, 3V66 Output Skew:............................................ 175 ps
SDRAM, APIC, 48-MHz Output Skew:........................ 250 ps
PCI Output Skew:........................................................ 500 ps
CPU to SDRAM Skew (@ 133 MHz) ....................... ± 0.5 ns
CPU to SDRAM Skew (@ 100 MHz) ................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz) ........................ 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead)........................... 1.5 to 3.5 ns
PCI to APIC Skew ..................................................... ± 0.5 ns
Block Diagram
X1
X2
SDATA
SCLK
(FS0:4*)
XTAL
OSC
PLL REF FREQ
SMBus
Logic
Divider,
Delay,
and
Phase
Con-
trol
Logic
PLL 1
PWR_DWN#
PLL2
/2
VDDQ3
REF2X/FS3*
VDDQ2
CPU0:1
2
APIC
VDDQ3
3V66_0:2
2
PCI0/FS0*
PCI1/FS1*
PCI2/FS2*
PCI3:6
5
SDRAM0:8
9
VDDQ3
48MHz_0
48MHz_1/FS4*
SI0/24_48#MHz*
Table 1. Frequency Selections
FS4 FS3 FS2 FS1 FS0 CPU SDRAM 3V66 PCI APIC SS
0 0 0 0 0 75.3 113.0 75.3 37.6 18.8 OFF
0 0 0 0 1 95.0 95.0 63.3 31.6 15.8 –0.6%
0 0 0 1 0 129.0 129.0 86.0 43.0 21.5 OFF
0 0 0 1 1 150.0 113.0 75.3 37.6 18.8 OFF
0 0 1 0 0 150.0 150.0 75.0 37.5 18.7 OFF
0 0 1 0 1 110.0 110.0 73.0 36.6 18.3 OFF
0 0 1 1 0 140.0 140.0 70.0 35.0 17.5 OFF
0 0 1 1 1 144.0 108.0 72.0 36.0 18.0 OFF
0 1 0 0 0 68.3 102.5 68.3 34.1 17.0 OFF
0 1 0 0 1 105.0 105.0 70.0 35.0 17.5 OFF
0 1 0 1 0 138.0 138.0 69.0 34.5 17.0 OFF
0 1 0 1 1 140.0 105.0 70.0 35.0 17.5 OFF
0 1 1 0 0 66.8 100.2 66.8 33.4 16.7 ±0.45%
0 1 1 0 1 100.2 100.2 66.8 33.4 16.7 ±0.45%
0 1 1 1 0 133.6 133.6 66.8 33.4 16.7 ±0.45%
0 1 1 1 1 133.6 100.2 66.8 33.4 16.7 ±0.45%
1 0 0 0 0 157.3 118.0 78.6 39.3 19.6 OFF
1 0 0 0 1 160.0 120.0 80.0 40.0 20.0 OFF
1 0 0 1 0 146.6 110.0 73.3 36.6 18.3 OFF
1 0 0 1 1 122.0 91.5 61.0 30.5 15.2 –0.6%
1 0 1 0 0 127.0 127.0 84.6 42.3 21.1 OFF
1 0 1 0 1 122.0 122.0 81.3 40.6 20.3 –0.6%
1 0 1 1 0 117.0 117.0 78.0 39.0 19.5 OFF
1 0 1 1 1 114.0 114.0 76.0 38.0 19.0 OFF
1 1 0 0 0 80.0 120.0 80.0 40.0 20.0 OFF
1 1 0 0 1 78.0 117.0 78.0 39.0 19.5 OFF
1 1 0 1 0 166.0 124.5 83.0 41.5 20.7 OFF
1 1 0 1 1 133.6 133.6 89.0 44.5 22.2 OFF
1 1 1 0 0 66.6 100.0 66.6 33.3 16.6 –0.6%
1 1 1 0 1 100.0 100.0 66.6 33.3 16.6 –0.6%
1 1 1 1 0 133.3 133.3 66.6 33.3 16.6 –0.6%
1 1 1 1 1 133.3 100.0 66.6 33.3 16.6 –0.6%
Pin Configuration^[1]
REF2x/FS3* 1
VDDQ3 2
X1 3
X2 4
GND 5
VDDQ3 6
3V66_0 7
3V66_1 8
3V66_2 9
GND 10
FS0*/PCI0 11
FS1*/PCI1 ₁₂
FS2*/PCI2 13
GND 14
PCI3 15
PCI4 16
VDDQ3 17
PCI5 18
PCI6 19
GND 20
48MHz_0 21
FS4*/48MHz_1 22
SI0/24_48#MHz* 23
VDDQ3 24
48 VDDQ2
47 APIC
46 VDDQ2
45 CPU0
44 CPU1
43 GND
42 VDDQ3
41 SDRAM0
40 SDRAM1
39 SDRAM2
38 GND
37 SDRAM3
36 SDRAM4
35 SDRAM5
34 VDDQ3
33 SDRAM6
32 SDRAM7
31 SDRAM8
30 GND
29 PWR_DWN#^
28 SCLK
27 VDDQ3
26 GND
25 SDATA
Note:
1. Internal 250K pull-down or pull up resistors present on inputs marked
with * or ^ respectively. Design should not rely solely on internal
pull-up or pull down resistor to set I/O pins HIGH or LOW respectively.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
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