W219B Datasheet, PDF (4/14 Pages) Cypress Semiconductor – Frequency Generator for Integrated Core Logic with 133-MHz FSB

W219B
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC
CPU 100 Period
Hub-PC
SDRAM 100 Period
Figure 3. Group Offset Waveforms (100.2 CPU Clock, 100.2 SDRAM Clock)
Power-Down Control
W219B provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
0 ns
1
VCO Internal
CPU 100MHz
3V66 66MHz
25 ns
50 ns
2
75 ns
Center
APIC 33MHz
PCI 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
Figure 4. PWRDWN# Timing Diagram^{[2, 3, 4, 5]}
Notes:
2. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
3. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W219B.
4. The shaded sections on the SDRAM, REF, and USB clocks indicate “Don’t Care” states.
5. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Rev 1.0, November 20, 2006
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