S29AS008J Datasheet, PDF (37/55 Pages) SPANSION – 8 Megabit (1M x 8-Bit / 512K x 16-Bit) CMOS 1.8 Volt-Only Boot Sector Flash Memory

Data Sheet
12.3
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (see DQ7: Data# Polling on page 35).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
algorithm is complete.
Table 12.1 on page 39 shows the outputs for Toggle Bit I on DQ6. Figure 12.2 on page 38 shows the toggle
bit algorithm in flowchart form, and Reading Toggle Bits DQ6/DQ2 on page 38 explains the algorithm.
Figure 18.8 on page 48 shows the toggle bit timing diagrams. Figure 18.9 on page 48 shows the differences
between DQ2 and DQ6 in graphical form. See also DQ2: Toggle Bit II on page 37.
12.4
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure.
(The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 12.1 on page 39 to compare
outputs for DQ2 and DQ6.
Figure 12.2 on page 38 shows the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits
DQ6/DQ2 on page 38 explains the algorithm. See also DQ6: Toggle Bit I on page 37. Figure 18.8 on page 48
shows the toggle bit timing diagram. Figure 18.9 on page 48 shows the differences between DQ2 and DQ6 in
graphical form.
November 9, 2011 S29AS008J_00_09
S29AS008J
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