S29AS008J Datasheet, PDF (14/55 Pages) SPANSION – 8 Megabit (1M x 8-Bit / 512K x 16-Bit) CMOS 1.8 Volt-Only Boot Sector Flash Memory

Data Sheet
7. Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the device. Table 7.1 lists the device bus operations, the
inputs and control levels they require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 7.1 S29AS008J Device Bus Operations
DQ8–DQ15
Operation
Read
Write (Program/Erase)
Standby
CE# OE# WE#
L
LH
L
HL
V_CC ±
0.2 V
X
X
RESET#
H
H
V_CC ±
0.2 V
WP#
X
(Note 3)
H
Addresses
(Note 1)
A_IN
A_IN
X
DQ0–
DQ7
D_OUT
D_IN
BYTE#
= V_IH
D_OUT
D_IN
BYTE#
= V_IL
DQ8–DQ14 = High-Z,
DQ15 = A-1
High-Z High-Z
High-Z
Output Disable
L
HH
H
X
X
High-Z High-Z
High-Z
Reset
X
XX
L
X
X
High-Z High-Z
High-Z
Sector Group Protect
(Note 2)
L
HL
V_ID
Sector Address,
X
A6 = L, A3 = A2 = L, D_IN
X
A1 = H, A0 = L
X
Sector Group
Unprotect (Note 2)
L
HL
V_ID
Sector Address,
H
A6 = H, A3 = A2 = L, D_IN
X
A1 = H, A0 = L
X
Temporary Sector
Group Unprotect
X
XX
V_ID
H
A_IN
D_IN
D_IN
High-Z
Legend
L = Logic Low = V_IL, H = Logic High = V_IH, V_ID = 9.0–11.0 V, X = Don’t Care, A_IN = Address In, D_IN = Data In, D_OUT = Data Out
Notes
1. Addresses are A18:A0 in word mode (BYTE# = V_IH), A18:A-1 in byte mode (BYTE# = V_IL).
2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See Sector Group
Protection/Unprotection on page 19.
3. If WP# = V_IL, the two outermost boot sectors remain protected. If WP# = V_IH, the two outermost boot sector group protection depends on
whether they were last protected or unprotected. If WP# = V_HH, all sectors are unprotected.
7.1 Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are active and
controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
7.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to V_IL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at V_IH. The BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See Reading Array Data on page 28 for more information. Refer to the AC Read Operations on page 43 for
timing specifications and to Figure 18.1 on page 43 for the timing diagram. I_CC1 in DC Characteristics
on page 41 represents the active current specification for reading array data.
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S29AS008J
S29AS008J_00_09 November 9, 2011