S29AS008J Datasheet, PDF (22/55 Pages) SPANSION – 8 Megabit (1M x 8-Bit / 512K x 16-Bit) CMOS 1.8 Volt-Only Boot Sector Flash Memory

Data Sheet
7.14
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to Table 11.1 on page 33 for command definitions). In addition, the following
hardware data protection measures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during V_CC power-up and power-down transitions, or from system
noise.
7.14.1
7.14.2
Low V_CC Write Inhibit
When V_CC is less than V_LKO, the device does not accept any write cycles. This protects data during V_CC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and
the device resets. Subsequent writes are ignored until V_CC is greater than V_LKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when V_CC is greater than V_LKO.
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
7.14.3
7.14.4
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IH or WE# = V_IH. To initiate a write cycle,
CE# and WE# must be a logical zero (V_IL) while OE# is a logical one (V_IH).
Power-Up Write Inhibit
If WE# = CE# = V_IL and OE# = V_IH during power up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
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S29AS008J
S29AS008J_00_09 November 9, 2011