CXD1948R Datasheet, PDF (47/78 Pages) Sony Corporation – IEEE1394 Link Layer LSI for DVB and DSS

CXD1948R
6-4. Asynchronous Packet Reception
Basically, if there is room to write the packet in FIFO and the destination_ID matches, then asynchronous
packets are received. Receive is completed when the packet data is read from the ARF inside the CXD1948R
by the external microcomputer.
The CXD1948R raises an RxDta flag when a packet is received. (Normally, if the RxDta bit of the CFR
Interrupt Mask register (10h to 14h) is set at “1”, XINT goes low when a packet is received and this can be
detected.)
Next, the CFR Async Status register (24h to 28h) ArfEmpty bit should be low. This indicates that a correct
packet was received.
After this, one quadlet at a time can be read by reading the CFR ATFWrite/ARFRead registers (74h to 78h).
Packet receive is completed by repeating this until the ArfEmpty bit goes high.
However, if the ARF status is empty, read will not be done even if Read is executed. In this case, the data read
by the microcomputer will be the previously read value.
The procedure for receiving a quadlet write request packet is given here as an example.
(for 8-bit data interface)
(1) Confirming that the packet was received
The CFR Interrupt register (0Ch to 0Fh) is read to confirm that the 25th bit (RxDta bit) is high.
XCS
ADDRESS
XW/R
0Ch
0Dh
0Eh
0Fh
DATA
82h
This indicates that RxDta only was generated.
(2) Confirming that the received packet was stored correctly in FIFO
The CFR Async Status register (24h to 27h) is read to confirm that the 26th bit (ArfEmpty bit) is low.
If this bit is high it means that reception may be in progress (all quadlets have not arrived). Read can not be
done in this state, so wait and then clear again.
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