CXD1948R Datasheet, PDF (37/78 Pages) Sony Corporation – IEEE1394 Link Layer LSI for DVB and DSS

CXD1948R
5) Cycle Timer Registers
These registers are composed of the 24.576MHz clock cycle Cycle Offset and the 125µs in its host, and the
Cycle Master that counts 1 second. The value of all nodes are regulated by the Cycle Master node.
The register address is 14h; it is read/write, and the initial value is 0000_0000h.
Bit
31 to 12
11 to 0
Name
CycleNumber
CycleOffset
Function
The upper 7 bits counts seconds (1Hz) and the lower 13 bits count the
isochronous cycle (8kHz = 125µs). The values are controlled by Control
register Cycle Master and Cycle Timer Enable.
Counts the system clock (24.576MHz). The Cycle Number is incremented
when this counter completes one cycle. The value is controlled by Control
register Cycle Master and Cycle Timer Enable.
6) DIF Mode Register
This register performs settings for transmit and receive of isochronous packets, and sets transmitted
isochronous packet 1394 header information (specified in the Draft).
The register address is 18h; it is read/write, and the initial value is 0100_0000h.
Bit
31
30
29
28
27
26
25
24
23 to 16
Name
IGFOn
IGFMode
HSTxOn
HSRxOn
IFClear
ErrBitEn
27MTS
LPS
RxChannel
Function
Isochronous FIFO operation is active at “1”
Changes isochronous FIFO operation to transmit at “1”. Receives at “0”
Isochronous transmit side operation is active at “1”. Invalid at “0”
Isochronous receive side operation is active at “1”. Invalid at “0”
Clears isochronous FIFO at “1”
Uses 27MHz time stamp at “1”
Does not use 27MHz time stamp at “0”
LPS pin high at “1”
LPS pin low at “0”
Tag/Channel Number for isochronous packet receive
7) IsoTxRx Init
This register performs setting related to isochronous packet transmit/receive time stamp, and packet size and
packet bank.
The register address is 1Ch; it is read/write, and the initial value is 0000_0000h.
Bit
26 to 16
13 to 9
8 to 0
Name
TxDelay
PacketBanks
S_PacketSize
Function
Transmission delay time for isochronous packets. The upper 6 bits are
added to the lower 6 bits of the Cycle Number, and the lower 5 bits are
added to the upper 5 bits of the Cycle Offset to obtain the time stamp.
Sets number of isochronous FIFO packet bank
Sets isochronous packet source packet size
The value includes SPH and additional data (byte units)
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