CXD1948R Datasheet, PDF (30/78 Pages) Sony Corporation – IEEE1394 Link Layer LSI for DVB and DSS

CXD1948R
Block Diagram
CXD1948R (transmit side)
host I/F
TxDelay
CFR
IEEE1394
Serial BUS
PACKETEN
transport stream data
DETECT
Cycle Timer
TimeStamp
MUX
Isochronous
FIFO
transmit
data _IEEE1394
PHY LSI
CXD1948R (receive side)
READREQ
transport stream data
DETECT
TimeStamp
Cycle Timer
DEMUX
Isochronous
FIFO
receive
data
IEEE1394
PHY LSI
5-10. Error Processing
When a correct packet can not be received, for example if a CRC error is generated or a packet which violates
protocol is received, the CXD1948R automatically performs error processing.
Error processing control is done by setting the CFR ErrOutEn register.
A description of error processing follows.
Processing for Transmit
ErrFlag input becomes valid when the CFR ErrBit Enable register is set to “1”.
The input error packet is processed in the same way as a normal packet.
However, error information is also transmitted, so only the mode when additional data is added to the transport
stream data is valid. (The superimposed position of the error information is the MSB of the additional data 3rd
byte.)
ErrFlag input becomes invalid when the ErrBitEnable register is set to “0”.
Processing for Receive
ErrFlag output becomes valid when the CFR ErrBit Enable register is set to “1”.
When the received isochronous packet is judged as an error, ErrFlag is made “1” and output.
Because the time stamp cannot be trusted, output is performed immediately.
When the ErrFlagEnable register is set to “0”, only the correctly received isochronous packets are output.
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