CXD1948R Datasheet, PDF (33/78 Pages) Sony Corporation – IEEE1394 Link Layer LSI for DVB and DSS

CXD1948R
Configuration Register (CFR) Address Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00
Version
Revision
Version
04
BusNumber
NodeNumber
NodeSum
CFMContID
Node Address
08
BsyCtrl
BlkBusDep ATRC
Control
0C
Interrupt
10
Interrupt Mask
14
CycleNumber
CycleOffset
Cycle Timer
18
RxChannel
DIF Mode
1C
TxDelay
PacketBanks
S_PacketSize
IsoTxRx Init
20
SIGapCnt
Diagnostics
24
ATAck
Async Status
28
PhyRegAd
PhyRegData
PhyAdRxReg
PhyDataRxReg
Phy Chip Access
2C
Parallel Port
30
NOSP
34
{ 0, 0 }
38
NODB
Tx1394Hdr
{Tag [1: 0] , ChNumber [5: 0] , 1394Rsv [1: 0 ] , Speed [1: 0 ] , sy [3 :0] }
TxCIPHdr1
{ DBS [7: 0], FN [1: 0], QPC [2: 0], SPH, rsv [1: 0] }
27Mrsv
TxCIPHdr2
{ 1, 0, FMT [5 : 0], TF, FDF [22 : 0] }
Tx1394Hdr
TxCIPHdr1
TxCIPHdr2
3C
SPH-reserved
AddSize
AddData2
AddData1
SPH-rsv/AddData1-2
40
AddData6
AddData5
AddData4
AddData3
AddData3-6
44
AddData10
AddData9
AddData8
AddData7
AddData7-10
48
Rx1394Hdr
Data_length [15 : 0] , Tag [1 : 0] , ChNumber [5 : 0]
Rx1394Hdr Rx1394Hdr
tCode [3 : 0] sy [3 : 0]
Rx1394Hdr
4C
RxCIPHdr1
EOH, form, SID [5 : 0] , DBS [7 : 0] , FN [1 : 0] , QPC [2 : 0] , SPH, rsv [1 : 0] , DBC [7 : 0]
RxCIPHdr1
50
RxCIPHdr2
EOH, form, TF, FMT [5 : 0] , FDF [22 : 0]
RxCIPHdr2
64
IPB Write (first quadlet of the packet)
68
IPB Write
6C
IPB Write (confirm write)
70
ATF Write (first quadlet of the packet)
74
ATF Write/ARF Read
78
7C
Note: The shaded areas (
ATF Write (confirm write)
) are reserved and can not be used.
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