LAN83C180 Datasheet, PDF (9/10 Pages) SMSC Corporation – 10/100 FAST ETHERNET PHY TRANSCEIVER

Migrating from the LAN83C180 10/100 PHY to the LAN83C185 10/100 PHY
7 General Considerations
The topics described in the following sub-sections below require additional attention by the systems
designer when changing from the LAN83C180 PHY to the LAN83C185 PHY.
7.1 Pinout Differences
The LAN83C180 and the LAN83C185 are not pin compatible. Always refer to the LAN83C185 datasheet
and LAN83C185 Customer Reference Board schematic when implementing a design using the LAN83C185.
7.1.1
PHY Address
The LAN83C185 has five PHY address signals (PHYAD0:4). The PHY address signals on the LAN83C185
are multiplexed with other signals (please refer to Table 7.1 below). The LAN83C180 provided these signals
on dedicated pins.
Table 7.1 - LAN83C185 PHY Address Pins
SIGNAL NAME
SPEED100 / PHYAD0
LINKON / PHYAD1
ACTIVITY / PHYAD2
FDUPLEX / PHYAD3
GPO1 / PHYAD4
LAN83C185 PIN NO’S.
16
17
19
20
2
Please refer to the LAN83C185 datasheet, “LED Description” section for proper PHY address/LED
implementation.
7.1.2
MII Interface
The MII interface functionality remains the same for both the LAN83C180 and the LAN83C185 – note that
the pin-outs are different. Please refer to the LAN83C185 datasheet for the proper pin numbers and
definitions.
The LAN83C185 incorporates series resistors between the LAN83C185 outputs and the MII interface inputs.
These signals are listed in Table 7.2 below.
Table 7.2 - LAN83C185 MII Series Terminations
SIGNAL NAME
MDIO
RXD0:3
RX_DV
RX_CLK
RX_ER
TX_CLK
COL
CRS
LAN83C185 PIN NO’S.
26
32, 31, 30, 29
33
34
35
38
47
48
Additionally, the MDIO signal (pin 26 on the LAN83C185) should be pulled to +5V via a 1.5K-Ohms resistor.
SMSC AN 10.13
Page 9
APPLICATION NOTE
Revision 1.2 (07-12-04)