LAN83C180 Datasheet, PDF (10/10 Pages) SMSC Corporation – 10/100 FAST ETHERNET PHY TRANSCEIVER

Migrating from the LAN83C180 10/100 PHY to the LAN83C185 10/100 PHY
7.1.3
RBIAS
The LAN83C180 incorporates two (2) RBIAS resistors on signals TXREF100 and TXREF10 (Pins 33, 34).
The LAN83C185 combines these onto one RBIAS signal - EXRES1 (Pin 59). The RBIAS resistor value for
the LAN83C185 is 12.4K-Ohm.
7.1.4
Mode
The Mode pins control the auto-negotiation, 10 and 100 Mbps data rates, and full-/half-duplex operation of
the LAN83C185 PHY.
The LAN83C180 utilizes two (2) pins - RPTR (Pin 21) and ANEN (Pin 22) which are analogous to the
LAN83C185’s MODE pins (Pins 4, 5, and 6).
Please refer to the LAN83C185 datasheet, “Mode Bus” paragraph, in the “Configuration Signals” section for
proper Mode bus operation.
8 Application Specific Notes
When designing the LAN83C185 with the SMSC LAN91C110 device, an extra single OR-GATE is required.
The OR-GATE should be wired with CRS and RX_DV signals (from the LAN83C185) to the inputs of the
OR-GATE. The output of the OR-GATE should be wired to the CRS100 pin of the LAN91C110.
LAN91C110
LAN83C185
CRS100
CRS
RX_DV
9 Conclusion
Following the guidelines in this application note will help to ensure a proper design-in when migrating from
the LAN83C180 to the LAN83C185
Note that this application note serves only as a general set of guidelines that should be followed when using
an SMSC LAN83C185 chip. Specific customer requirements may both create new guidelines, which must be
followed, and/or force specific rules dictated here to be broken.
SMSC AN 10.13
Page 10
APPLICATION NOTE
Revision 1.2 (07-12-04)