LAN83C180 Datasheet, PDF (5/10 Pages) SMSC Corporation – 10/100 FAST ETHERNET PHY TRANSCEIVER

Migrating from the LAN83C180 10/100 PHY to the LAN83C185 10/100 PHY
3 Power Requirements
The LAN83C185 requires a +3.3V power source, which may be obtained from any existing on-board +3.3V
source, or, if none is available, by incorporating an external regulator such as the Linear Technologies
LT1086 +5V-input to +3.3V-output fixed-voltage regulator - into the LAN83C185 design.
The +3.3V regulator output is supplied to the LAN83C185 core via the pins listed in Table 3.1 below:
Table 3.1 – LAN83C185 Power Pins
SIGNAL NAME
VDD
AVDD
VREG
LAN83C185 PIN NO’S.
8, 18, 43
53, 57, 61, 63
13
It is recommended that all VDD, AVDD, and VREG signals on the LAN83C185 be supplied +3.3V from the
board’s power plane via three ferrite beads (one per signal group – see Figure 3.1 below).
+3.3V
FB1
FB2
FB3
LAN83C185
Figure 3.1 - Power Pin Connections - LAN83C185 to +3.3V
SMSC AN 10.13
Page 5
APPLICATION NOTE
Revision 1.2 (07-12-04)