LPC47M112 Datasheet, PDF (67/208 Pages) SMSC Corporation – ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE

Enhanced Super I/O Controller with LPC Interface
Datasheet
FIFO
MODE
ONLY
BIT 3
0
0
INTERRUPT
IDENTIFICATION
REGISTER
BIT 2 BIT 1 BIT 0
0
1
0
0
0
0
INTERRUPT SET AND RESET FUNCTIONS
PRIORITY INTERRUPT
LEVEL
TYPE
INTERRUPT
SOURCE
INTERRUPT
RESET
CONTROL
Indication
Removed From or
Input to the RCVR
FIFO during the
last 4 Char times
and there is at
least 1 char in it
during this time
Register
Third
Transmitter
Transmitter
Holding
Holding Register
Register Empty Empty
Reading the IIR
Register (if Source
of Interrupt) or
Writing the
Transmitter
Holding Register
Fourth
MODEM
Status
Clear to Send or Reading the
Data Set Ready or MODEM Status
Ring Indicator or Register
Data Carrier
Detect
LINE CONTROL REGISTER (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
Start LSB Data 5-8 bits MSB Parity Stop
SMSC DS – LPC47M112
Page 67
Rev. 02/02/2005